Memory Device Having Wide Area Phase Change Element and Small Electrode Contact Area

ABSTRACT

A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

PARTIES TO A JOINT RESEARCH AGREEMENT

International Business Machines Corporation, a New York corporation,Macronix International Corporation, Ltd., a Taiwan corporation, andInfineon Technologies A.G., a German corporation, are parties to a JointResearch Agreement

BACKGROUND

1. Field of the Invention

This invention relates to high density memory devices based on phasechange based memory materials, including chalcogenide based materialsand other materials, and to methods for manufacturing such devices.

2. Description of Related Art

Phase change based memory materials are widely used in read-writeoptical disks. These materials have at least two solid phases, includingfor example a generally amorphous solid phase and a generallycrystalline solid phase. Laser pulses are used in read-write opticaldisks to switch between phases and to read the optical properties of thematerial after the phase change.

Phase change based memory materials, like chalcogenide based materialsand similar materials, also can be caused to change phase by applicationof electrical current at levels suitable for implementation inintegrated circuits. The generally amorphous state is characterized byhigher resistivity than the generally crystalline state; this differencein resistance can be readily sensed to indicate data. These propertieshave generated interest in using programmable resistive material to formnonvolatile memory circuits, which can be read and written with randomaccess.

The change from the amorphous to the crystalline state is generally alower current operation. The change from crystalline to amorphous,referred to as reset herein, is generally a higher current operation,which includes a short high current density pulse to melt or breakdownthe crystalline structure, after which the phase change material coolsquickly, quenching the phase change process, allowing at least a portionof the phase change structure to stabilize in the amorphous state. It isdesirable to minimize the magnitude of the reset current used to causetransition of phase change material from crystalline state to amorphousstate. The magnitude of the reset current needed for reset can bereduced by reducing the size of the phase change material element in thecell and by reducing the size of the contact area between electrodes andthe phase change material, so that higher current densities are achievedwith small absolute current values through the phase change materialelement.

One direction of development has been toward forming small pores in anintegrated circuit structure, and using small quantities of programmableresistive material to fill the small pores. Patents illustratingdevelopment toward small pores include: Ovshinsky, “Multibit Single CellMemory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issuedNov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic]Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan etal., “Controllable Ovonic Phase-Change Semiconductor Memory Device andMethods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov.21, 2000.

Problems have arisen in manufacturing such devices with very smalldimensions, and with variations in process that meet tightspecifications needed for large-scale memory devices. It is desirabletherefore to provide a memory cell structure having small dimensions andlow reset currents, and a method for manufacturing such structure

SUMMARY

Generally, the invention features a memory cell device of the type thatincludes a memory material switchable between electrical property statesby application of energy, situated between first and second (“bottom”and “top”) electrodes. In embodiments of a memory cell device of theinvention, the top electrode includes a larger body portion and a stemportion. The memory material is disposed as a layer over a bottomelectrode layer, and a base of the stem portion of the top electrode isin electrical contact with a small area of the surface of the memorymaterial. The area of electrical contact is defined by the dimensions ofthe stem of the electrode, near the base, and not by the dimensions ofthe memory material, which can have a significantly greater area. Thedimensions of the stem portion of the top electrode, and of the area ofcontact of the base of the stem with the memory material can accordingto the invention be made very small, and are not dependent upon maskingtechnologies.

In one general aspect, the invention features a memory cell deviceincluding a bottom electrode, a memory material element over the bottomelectrode, and a top electrode including a body portion and a stemportion, in which a base of the stem portion of the top electrode is inelectrical contact with a small area of a surface of the memorymaterial.

In another general aspect the invention features a method for making amemory cell device, by: forming a bottom electrode layer over a surfaceof a substrate; forming a memory material layer over the bottomelectrode layer; forming a cap layer over the memory material layer;patterning the bottom electrode layer, the memory material layer and thecap layer to define a bottom electrode overlain by a memory elementoverlain by a cap; forming an intermetal dielectric fill layer over thememory material; forming an etch stop layer over the dielectric fill;forming a via through the etch stop layer and the dielectric fill toexpose a surface of the cap, the via including an opening in the etchstop layer; removing a quantity of dielectric fill material from wallsof the via, forming a cavity and resulting in an undercut beneath themargin of the opening in the etch stop layer; depositing a thermalisolation material in the cavity over the surface of the memorymaterial, whereby a void is formed in the thermal isolation material;anisotropically etching the thermal isolation material and the cap toexpose a small area of the surface of the memory material, forming apore in the thermal isolation material and the cap adjacent the memoryelement and a wider cavity in the thermal isolation material; anddepositing an electrode material in the pore and the wider cavity toform the top electrode.

According to the invention, a masking step establishes the openings inthe silicon nitride layer over the memory cell vias. The remainder ofthe process is self-aligning, and highly repeatable. The area of contactbetween the top electrode and the memory material is determined by widthof the stem portion of the top electrode, which in turn is determined byanisotropic etch conditions and by the size and shape of the void in thethermal insulator, which can be readily and repeatably controlled.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic sketch in a sectional view showing a memorycell device according to an embodiment of the invention.

FIGS. 2-10 are sketches in a sectional view showing stages in a processfor making a phase change memory cell according to an embodiment of theinvention.

FIGS. 11A and 11B are sketches in a sectional view showing a portion ofa memory array according to an embodiment of the invention; FIG. 11Bshows a programming current flow.

FIG. 12 is a schematic diagram for a memory array having phase changememory elements.

FIG. 13 is a diagrammatic sketch in a layout or plan view showing a partof a memory array having phase change memory elements.

DETAILED DESCRIPTION

The invention will now be described in further detail by reference tothe drawings, which illustrate alternative embodiments of the invention.The drawings are diagrammatic, showing features of the invention andtheir relation to other features and structures, and are not made toscale. For improved clarity of presentation, in the FIGs. illustratingembodiments of the invention, features corresponding to features shownin other drawings are not all particularly renumbered, although they areall readily identifiable in all the FIGs.

Turning now to FIG. 1, there is shown generally at 10 a memory cellstructure according to an embodiment of the invention. Memory cellstructure 10 includes a bottom electrode 12 overlain by a memory element14, a top electrode 18 including a body portion 19 and a stem portion17. The stem portion 17 of the top electrode 18 is in contact with asmall area 13 of the surface 15 of the memory material layer 14. The topelectrode may optionally include a core portion 21 and a liner (heater)portion 23. The top electrode 18 is surrounded by a thermal isolationmaterial 16. The top electrode and the surrounding thermal isolationmaterial are formed within a via in an interlayer dielectric fill, orseparation layer, 11, which is overlain by an electrically insulativelayer 20.

The memory cell structure 10 is formed over a semiconductor substrateincluding access transistors, and electrical connection of the surface22 of the top electrode 18 is made by way of patterned metallization, asdescribed for example below with reference to FIG. 11A.

The conductive path in the memory cell passes from the surface 22 of thetop electrode 18 through the top electrode body portion 19 and the topelectrode stem portion 17 and then into the memory element 14 at thearea of contact 13 of the base of the stem portion 17 with the surfaceof the memory element 14, then through the memory element to the bottomelectrode 12.

This memory cell structure according to the invention provides severaladvantageous features. The top electrode is well isolated thermally fromthe surrounding dielectric fill. The area of contact of the topelectrode with the memory material is small, so that the reset programcurrent can be reduced. The area of contact between the top electrodeand the memory material is determined by width of the stem portion ofthe top electrode, which in turn is determined by anisotropic etchconditions and by the size and shape of the void in the thermalinsulator. The size of the void in the thermal insulator is determinedby the width of an undercut 320 at the margin of the opening in theelectrically insulative layer, which can be readily and repeatablycontrolled.

Embodiments of memory cell device 10 include phase change based memorymaterials, including chalcogenide based materials and other materials,for memory material 14. Phase change alloys are capable of beingswitched between a first structural state in which the material is in agenerally amorphous solid phase, and a second structural state in whichthe material is in a generally crystalline solid phase in its localorder in the active channel region of the cell. These alloys are atleast bistable. The term amorphous is used to refer to a relatively lessordered structure, more disordered than a single crystal, which has thedetectable characteristics such as higher electrical resistivity thanthe crystalline phase. The term crystalline is used to refer to arelatively more ordered structure, more ordered than in an amorphousstructure, which has detectable characteristics such as lower electricalresistivity than the amorphous phase. Typically, phase change materialsmay be electrically switched between different detectable states oflocal order across the spectrum between completely amorphous andcompletely crystalline states. Other material characteristics affectedby the change between amorphous and crystalline phases include atomicorder, free electron density and activation energy. The material may beswitched either into different solid phases or into mixtures of two ormore solid phases, providing a gray scale between completely amorphousand completely crystalline states. The electrical properties in thematerial may vary accordingly.

Phase change alloys can be changed from one phase state to another byapplication of electrical pulses. It has been observed that a shorter,higher amplitude pulse tends to change the phase change material to agenerally amorphous state. A longer, lower amplitude pulse tends tochange the phase change material to a generally crystalline state. Theenergy in a shorter higher amplitude pulse is high enough to allow forbonds of the crystalline structure to be broken and short enough toprevent the atoms from realigning into a crystalline state. Appropriateprofiles for pulses can be determined, without undue experimentation,specifically adapted to a particular phase change alloy. In thedisclosure herein, the phase change material is referred to as GST, andit will be understood that other types of phase change materials can beused. A material useful for implementation of a memory device describedherein is Ge₂Sb₂Te₅.

With reference again to FIG. 1, access circuitry, such as described withreference to FIG. 12, can be implemented to contact the first electrode12 and the second electrode 18 in a variety of configurations forcontrolling the operation of the memory cell, so that it can beprogrammed to set the phase change material 14 in one of the two solidphases that can be reversibly implemented using the memory material. Forexample, using a chalcogenide-based phase change memory material, thememory cell may be set to a relatively high resistivity state in whichat least a portion of the bridge in the current path is an amorphousstate, and a relatively low resistivity state in which most of thebridge in the current path is in a crystalline state. For example,application of an electrical pulse having a suitable shorter, highamplitude profile, for example, results in changing the phase changematerial 14 locally to a generally amorphous state, as indicated at 29in FIG. 1.

Manufacture of a memory cell device 10 will be described with referenceto FIGS. 2-10, in which various stages in an exemplary process are shownin sectional view.

Referring to FIG. 2, a layer 212 of a material suitable as a bottomelectrode is formed over a surface 211 of a substrate 210; a layer 214of a phase change memory material is formed over the bottom electrodematerial layer 212; and a layer 226 of a protective cap material isformed over the layer 214 of phase change memory material.

The bottom electrode material layer 212 may be formed by a thin filmdeposition technique such as, for example, sputtering or atomic layerdeposition onto surface 211 of the substrate 210. A suitable bottomelectrode layer 212 may include layers of two or more materials,selected for their properties, among others, of adhesion to materials onadjacent layers. The bottom electrode layer 212 may include, forexample, a film of titanium, followed by a film of titanium nitride onthe surface of the titanium film. Titanium adheres well to materials inthe underlying semiconductor substrate (such as a silicide); andtitanium nitride adheres well to the overlying GST phase changematerial. Additionally, titanium nitride serves as a good diffusionbarrier. A wide variety of materials can be used for the bottomelectrode, including for example Ta, TaN, TiAlN, TaAlN; or the materialof the bottom electrode may include one or more elements selected fromthe group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni and Ru,and alloys thereof; or may include a ceramic. The conditions of thedeposition processes are established to provide suitable thickness of,and coverage by, the material(s) of the electrode layer, and to providegood thermal isolation. The bottom electrode at the surface of thesubstrate may have a thickness in a range about 200 nm to about 400 nm.

The layer 214 of phase change memory material may be formed over thebottom electrode layer 212 by a thin film deposition technique such as,for example, sputtering or atomic layer deposition. The conditions ofthe deposition processes are established to provide a suitable thicknessof the phase change material layer over the bottom electrode. The phasechange material layer at the surface of the bottom electrode over thesubstrate may have a thickness in a range about 20-200 nm.

The protective cap layer 226 protects the underlying phase change memorymaterial during subsequent processes. Suitable materials for theprotective cap layer 226 include, for example, silicon nitride, SiO₂,Al₂O₃, Ta₂O₅, and the layer may be formed by, for example a CVD or PVDprocess. The protective cap layer 226 may have a thickness in the rangeabout 5 nm to about 50 nm. Formation of the bottom electrode layer, thephase change memory material layer, and the protective cap layer resultsin a structure as shown in FIG. 2

Then a mask and etch process is used to define a bottom electrode 12overlain by a phase change material element 14 and a cap 326approximately at the site 30 of the memory cell, resulting in astructure as shown in FIG. 3. The cap 326, which has a surface 315,protects the phase change material element during the mask and etchprocess and, particularly, in some embodiments, during removal(stripping) of the photoresist.

Then, an interlayer dielectric fill is formed over the surface of thesubstrate and over the patterned bottom electrode, memory element, andcap, and an etch stop layer is formed over the interlayer dielectricfill. The interlayer dielectric fill may include, for example, a low-Kdielectric material such as silicon dioxide, silicon oxynitride, siliconnitride, Al₂O₃, or other low K dielectric. Alternatively, the materialof the interlayer dielectric fill may include one or more elementsselected from the group consisting of Si, Ti, Al, Ta, N, O, and C. Thematerial of the etch stop layer may include, for example, siliconnitride. Vias are formed through the etch stop layer and the dielectricfill, using a mask and etch process. FIG. 4 shows a resulting memorycell via 200, formed through the etch stop layer 20, and the dielectricfill layer 211. The via reaches to the surface 315 of the cap 326 overthe phase change material element 14. Then, a wet etch process, such as,for example, a hydrofluoric acid dip, is applied to undercut thedielectric fill material and to widen the cavity 300 in the dielectricfill 11, as shown in FIG. 5.

The dimensions of the completed memory cell will be determined in partby the dimensions of the memory cell via and, particularly, in part bythe extent of the undercut, as described with reference particularly toFIGS. 6 and 7, below.

The interlayer dielectric fill may have a thickness in a range about 100nm to about 300 nm, and the silicon nitride layer may have a thicknessin a range about 10 nm to about 40 nm. The via 200 may have a width in arange about 30 nm to about 300 nm. The size of the opening 220 throughthe silicon nitride layer is established, within a variation (typically+/−about 20 nm for example), by the design rules for the particularlithographic process used to form the via 200. The diameter 220 of theopening in the silicon nitride layer may be generally circular, forexample, with a diameter 220 about 200 nm+/−about 20 nm, for example.The material of the etch stop layer 20 is selected to be selectivelyetched relative to the dielectric fill material; that is, the wet etchprocess that removes the dielectric material to form the undercut 320may have substantially no effect on the etch stop layer 20. Wheresilicon dioxide is the dielectric fill material, for example, siliconnitride provides a suitable material for the etch stop layer. The extentof the undercut can be controlled by timing the wet etch process, withina variation typically +/−about 1.5 nm, for example. The conditions ofthe wet etch are established to provide an undercut 320 having a width321 in a range about 5 nm to about 50 nm beneath the margin in theopening of the silicon nitride layer, resulting in a width 311 of thecavity 300 about the sum of the width 220 of the opening in the siliconnitride layer plus 2 times the width 321 of the undercut 320.

The protective cap layer 326 may protect the underlying phase changememory element 14 during the etch process that forms the via 200, andduring the wet etch process that widens the cavity 300 in the dielectricfill.

Then a suitable thermal isolation material is formed over the structureof FIG. 5, and within the via, using a conformational deposition processsuch as a chemical vapor deposition (CVD), resulting in a structure asshown FIG. 6. The geometry of the undercut, and the conditions of thedeposition process, result in formation of a void 610 in the thermalisolation material 600. The void 610 is approximately centered withinthe cavity in the memory cell via. The shape and width 613 of the void(or diameter, where the void is generally round, for example circular)is related to the width of the undercut 320; for example, where theopening 220 in the etch stop layer 20 is generally circular, forexample, the void can be expected to be generally circular, and can beexpected to have a diameter 613 about two times the width of theundercut 321.

Suitable thermal isolation materials 600 include dielectric materials,and may be an oxide, such as a silicon dioxide, for example. Otherthermal isolation materials may be preferred, and selection of a thermalisolation material depends in part on the material of the interlayerdielectric fill; particularly, thermal isolation material 600 is abetter thermal insulator than the interlayer dielectric fill 11,preferably at least 10% better. Therefore, when the interlayerdielectric comprises silicon dioxide, the thermal insulator 600preferably has a thermal conductivity value “kappa” less than that ofsilicon dioxide, which is 0.014 J/cm*K*sec. Representative materials forthermal insulator 600 include low permittivity (low-K) materials,including materials that are a combination of the elements silicon (Si),carbon (C), oxygen (O), fluorine (F), and hydrogen (H). Examples ofthermally insulating materials which are candidates for use as thermalinsulator 600 include SiCOH, polyimide, polyamide, and fluorocarbonpolymers. Other examples of materials which are candidates for use forthermal insulator 600 include fluorinated SiO₂, silsesquioxane,polyarylene ethers, parylene, fluoropolymers, fluorinated amorphouscarbon, diamond like carbon, porous silica, mesoporous silica, poroussilsesquioxane, porous polyimide, and porous polyarylene ethers. Asingle layer or combination of layers can provide thermal insulation. Inother preferred embodiments, the thermal insulator has a thermalconductivity less than that of the amorphous state of the phase changematerial, that is, less than about 0.003 J/cm*K*sec where the phasechange material is a GST.

Then an anisotropic etch is performed, such as a reactive ion etch, toremove some of the thermal isolation material. The etch proceeds untilan area of the surface of the cap 316 is exposed, and then proceedsuntil an area 13 of the surface 15 of the phase change element 14 isexposed. In some embodiments a first etch is performed under conditionsthat remove the thermal isolation material, and a second etch isperformed under conditions that remove a portion of the cap (differentetch chemistries may be used, for example). FIG. 7 shows a resultingstructure. All the thermal isolation material overlying the etch stoplayer 20 has been removed; and some of the thermal isolation materialhas been removed from the cavity in the memory cell via forming a pore712 near the surface of the phase change material, which will define thestem portion of the top electrode; and a wider cavity 710, which willdefine the body portion of the top electrode The undercut 320 protectsthe thermal isolation material beneath it, leaving a residual portion720 adjacent the wall of the cavity and adjacent the portion of thephase change material next to the wall of the cavity. The etch isstopped when a small area 13 of the surface of the phase change materialis exposed at the bottom of the pore 712; a residual portion 722 remainsafter the etch is stopped, and this defines the shape and dimensions ofthe pore 712. The dimensions of the stem portion of the topelectrode—and, consequently, the area of the contact of the topelectrode with the phase change material—are determined in part by theposition and the size of the void and by the deposition conformality ofthe thermal insulator material 600. Particularly, the width of theexposed small area 13 (diameter, if the area is circular, for example)of the phase change material 14 exposed at the bottom of the pore 712results from the shape and width 713 of the pore 712, which in turnresults from the shape and size of the void, as well as from theconditions of the etch. As noted above, the width (or diameter) of thevoid relates to the width of the undercut, and is not dependent upon thewidth of the via; typically the width of the void is about twice thewidth of the undercut. The position of the void (and, consequently, theposition of the pore 712) is approximately at the center of the via and,because the memory material element has a significantly greater area, itis not necessary for the via to be precisely aligned with the memorymaterial element.

The exposed small area 13 need not have any particular shape; it may,for example, be generally round (e.g., circular) or it may have someother shape, or it may have an irregular shape. Where the small area iscircular, for example, the small area 13 may have a diameter in a rangeabout 10 nm to about 100 nm, such as about 20 nm to about 50 nm, forexample about 30 nm. Under conditions described herein, these dimensionsmay be expected where the width of the undercut is in a range about 5 nmto about 50 nm, such as about 10 nm to about 25 nm, for example about 15nm.

Then the top electrode is formed in the memory cell cavity. Inembodiments as shown in the FIGs., the top electrode includes a coresurrounded by a liner (heater). In such embodiments, the liner is formedby depositing a suitable liner material over the structure of FIG. 7,resulting in a structure as shown in FIG. 8. The liner material fillsthe pore 712, forming the stem portion 17 of the top electrode; andforms a film 723 over the other surfaces of the structure. Suitableliner materials include, for example, tantalum nitride, titaniumnitride, tungsten nitride, TiW. The conditions of the depositionprocesses are established to provide suitable thickness of, and coverageby, the material(s) of the electrode layer. Then the core of the topelectrode is formed by depositing a suitable electrode material withinthe cavity and over the structure of FIG. 7, as shown at 900 in FIG. 9.The core material may be deposited by, for example, chemical vapordeposition (CVD). The top electrode 900 may be, for example, tungsten.Other suitable top electrode core materials include, for example, othermetals such as copper, platinum, ruthenium, iridium, and alloys thereof.

A wide variety of materials can be used for the top electrode, includingfor example Ta, TaN, TiAlN, TaAlN; or the material of the top electrodemay include one or more elements selected from the group consisting ofTi, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni and Ru, and alloys thereof; or mayinclude a ceramic.

Then a planarizing process is used to remove the upper material, down tothe surface 922 of the silicon nitride layer 20, resulting in acompleted memory cell structure as shown in FIG. 10.

FIG. 11A shows a sectional view of two phase change random access memorycells 100, 102 according to the invention. The cells 110, 102 are formedon a semiconductor substrate 110. Isolation structures such as shallowtrench isolation (“STI”) dielectric trenches 112 isolate pairs of rowsof memory cell access transistors in the substrate. The accesstransistors are formed by common source region 116 in the substrate 110,and drain regions 115 and 117 in the substrate 112. Polysilicon wordlines 113 and 114 constitute the gates of the access transistors. Commonsource line 119 is formed over the source region 116. A first dielectricfill layer 111 is deposited over the polysilicon word lines and thecommon source line on the substrate 110. Contact plugs 103, 104 (e.g.,tungsten) are formed in vias in the fill layer 111 over the drainregions. Memory cells 100, 102 are formed, generally as described abovewith reference to FIGS. 2-10, and the memory cells 101, 102 arestructured generally each like memory cell 10 as described withreference to FIG. 1: a bottom electrode material layer is deposited overthe first dielectric fill layer, a memory material layer is depositedover the bottom electrode material layer, and a protective cap materiallayer is deposited over the memory material layer; the layers arepatterned to form bottom electrode in contact with the contact plug,memory elements over the bottom electrode, and a cap over the memoryelement; a second dielectric fill layer 121 is deposited over thesestructures, an etch stop layer 120 is deposited over the seconddielectric fill layer, and the etch stop layer and second dielectricfill are masked and etched to form vias and then wet etched to formcavities with undercuts beneath the margins of the via openings in theetch stop layer; then the thermal isolation material is deposited in thecavities (forming voids), anisotropic etch is formed through the thermalisolation material and the cap to form a cavity and to expose a smallarea of the surface of the memory element; the top electrode is formedin the cavity; the upper surface of the structure is planarized, and bitline 141 is formed over the memory cells, in contact with the uppersurfaces of the top electrodes.

FIG. 11B shows a programming current path (arrow 129) through memorycells according to the invention, as described with reference to FIGS. 1and 11A. The current flows from the M1 common source line 119 to thesource region 116, then to the drain region 115, and from the drainregion 115 through the contact plug 103 to the memory cell 100 andthrough the memory cell 100 to the bit line 141.

FIG. 12 is a schematic illustration of a memory array, which can beimplemented as described herein. In the schematic illustration of FIG.2, a common source line 128, a word line 123 and a word line 124 arearranged generally parallel in the Y-direction. Bit lines 141 and 142are arranged generally parallel in the X-direction. Thus, a Y-decoderand a word line driver in block 145 are coupled to the word lines 123,124. An X-decoder and a set of sense amplifiers in block 146 are coupledto the bit lines 141 and 142. The common source line 128 is coupled tothe source terminals of access transistors 150, 151, 152 and 153. Thegate of access transistor 150 is coupled to the word line 123. The gateof access transistor 151 is coupled to the word line 124. The gate ofaccess transistor 152 is coupled to the word line 123. The gate ofaccess transistor 153 is coupled to the word line 124. The drain ofaccess transistor 150 is coupled to the bottom electrode member 132 formemory cell 135, which has top electrode member 134. The top electrodemember 134 is coupled to the bit line 141. Likewise, the drain of accesstransistor 151 is coupled to the bottom electrode member 133 for memorycell 136, which has top electrode member 137. The top electrode member137 is coupled to the bit line 141. Access transistors 152 and 153 arecoupled to corresponding memory cells as well on bit line 142. It can beseen that in this illustrative configuration the common source line 128is shared by two rows of memory cells, where a row is arranged in theY-direction in the illustrated schematic. In other embodiments, theaccess transistors can be replaced by diodes, or other structures forcontrolling current flow to selected devices in the array for readingand writing data.

FIG. 13 is a layout or plan view of a memory array as shown in theschematic diagram of FIG. 12, showing the structure above thesemiconductor substrate layer 110 of FIG. 11A. Certain of the featuresare omitted, or are shown as transparent. Word lines 123, 124 are laidout substantially parallel to the source line 28. Metal bit lines 141and 142 are laid out over, and substantially perpendicular to, the wordlines. The positions of memory cell devices 135 below the metal bitlines are indicated, although they would not be visible in this view.

Embodiments of memory cell device 10 include phase change based memorymaterials, including chalcogenide based materials and other materials,for memory material 14. Chalcogens include any of the four elementsoxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming partof group VI of the periodic table. Chalcogenides comprise compounds of achalcogen with a more electropositive element or radical. Chalcogenidealloys comprise combinations of chalcogenides with other materials suchas transition metals. A chalcogenide alloy usually contains one or moreelements from column six of the periodic table of elements, such asgermanium (Ge) and tin (Sn). Often, chalcogenide alloys includecombinations including one or more of antimony (Sb), gallium (Ga),indium (In), and silver (Ag). Many phase change based memory materialshave been described in technical literature, including alloys of: Ga/Sb,In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te,In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In thefamily of Ge/Sb/Te alloys, a wide range of alloy compositions may beworkable. The compositions can be characterized asTe_(a)Ge_(b)Sb_(100−(a+b)). One researcher has described the most usefulalloys as having an average concentration of Te in the depositedmaterials well below 70%, typically below about 60% and ranged ingeneral from as low as about 23% up to about 58% Te and most preferablyabout 48% to 58% Te. Concentrations of Ge were above about 5% and rangedfrom a low of about 8% to about 30% average in the material, remaininggenerally below 50%. Most preferably, concentrations of Ge ranged fromabout 8% to about 40%. The remainder of the principal constituentelements in this composition was Sb. These percentages are atomicpercentages that total 100% of the atoms of the constituent elements.(Ovshinsky '112 patent, columns 10-11.) Particular alloys evaluated byanother researcher include Ge₂Sb₂Te₅, GeSb₂Te₄ and GeSb₄Te₇. (NoboruYamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks forHigh-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) Moregenerally, a transition metal such as chromium (Cr), iron (Fe), nickel(Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloysthereof may be combined with Ge/Sb/Te to form a phase change alloy thathas programmable resistive properties. Specific examples of memorymaterials that may be useful are given in Ovshinsky '112 at columns11-13, which examples are hereby incorporated by reference.

The invention has been described with reference to phase changematerials. However, other memory materials, also sometimes referred toas programmable materials, can also be used. As used in thisapplication, memory materials are those materials having electricalproperties, such as resistance, that can be changed by the applicationof energy; the change can be a stepwise change or a continuous change ora combination thereof. Other programmable resistive memory materials maybe used in other embodiments of the invention, including N₂ doped GST,Ge_(x)Sb_(y), or other material that uses different crystal phasechanges to determine resistance; Pr_(x)Ca_(y)MnO₃, PrSrMnO, ZrOx, orother material that uses an electrical pulse to change the resistancestate; 7,7,8,8-tetracyanoquinodimethane (TCNQ), methanofullerene6,6-phenyl C61-butyric acid methyl ester (PCBM), TCNQ-PCBM, Cu-TCNQ,Ag-TCNQ, C60-TCNQ, TCNQ doped with other metal, or any other polymermaterial that has bistable or multi-stable resistance state controlledby an electrical pulse. Further examples of programmable resistivememory materials include GeSbTe, GeSb, NiO, Nb—SrTiO₃, Ag—GeTe, PrCaMnO,ZnO, Nb₂O₅, Cr—SrTiO₃.

For additional information on the manufacture, component materials, useand operation of phase change random access memory devices, see U.S.patent application Ser. No. 11/155,067, filed 17 Jun. 2005, titled “Thinfilm fuse phase change RAM and manufacturing method”.

Other embodiments are within the scope of the invention.

1. A memory device comprising a bottom electrode, a memory element overthe bottom electrode, and a top electrode including a body portion and astem portion, wherein a base of the stem portion of the top electrode isin electrical contact with a small area of a surface of the memoryelement.
 2. The device of claim 1 wherein the memory element comprises amemory material having at least two solid phases.
 3. The device of claim2 wherein the at least two solid phases are reversibly inducible by avoltage applied across the bottom and top electrodes.
 4. The device ofclaim 2 wherein the at least two solid phases include a generallyamorphous phase and a generally crystalline phase.
 5. The device ofclaim 2 wherein the memory material comprises an alloy including acombination of Ge, Sb, and Te.
 6. The device of claim 2 wherein thememory material comprises an alloy including a combination of two ormore materials from the group Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu,Pd, Pb, Ag, S, and Au.
 7. The device of claim 1 wherein the small areaof electrical contact has a width in a range about 10 nm to about 100nm.
 8. The device of claim 1 wherein the small area of electricalcontact has a width in a range about 20 nm to about 50 nm.
 9. The deviceof claim 1 wherein the small area of electrical contact has a widthabout 30 nm.
 10. The device of claim 1, the top electrode comprising amaterial chosen from Ta, TaN, TiAlN, TaAlN.
 11. The device of claim 1,the top electrode comprising a material chosen from Ti, W, Mo, Al, Ta,Cu, Pt, Ir, La, Ni and Ru, and alloys thereof.
 12. The device of claim1, the top electrode comprising a ceramic.
 13. The device of claim 1,the top electrode comprising a liner and a core.
 14. The device of claim13, the liner comprising a material chosen from tantalum nitride,titanium nitride, and tungsten nitride.
 15. The device of claim 13, thecore comprising a material chosen from W, Cu, Pt, Ru, Ir, and alloysthereof.
 16. A memory device, comprising: a substrate; an electrode overthe substrate; a memory element in electrical contact with theelectrode; a dielectric fill layer over the memory element, theelectrode, and the substrate, the dielectric fill layer having a cavityextending therethrough over the memory element, the cavity having awidth; an etch stop layer over the dielectric fill layer, the etch stoplayer having an opening therethrough over the dielectric fill cavity,the opening having a width less than the dielectric fill cavity widthsuch that a margin of the opening overhangs the dielectric fill cavity;and a second electrode in the dielectric fill cavity, the secondelectrode comprising a body portion and a stem portion, wherein a baseof the stem portion is in electrical contact with an area of a surfaceof the memory element; whereby the area of electrical contact has awidth related to a width of the overhang of the margin of the opening inthe etch stop layer.
 17. The memory device of claim 16 wherein the widthof the area of electrical contact is about twice the width of theoverhang of the margin of the opening in the etch stop layer.
 18. Thememory device of claim 16 wherein the second electrode is surrounded bya thermal isolation material in the dielectric fill cavity.
 19. Thememory device of claim 18 wherein the stem portion of the secondelectrode is situated within a pore in the thermal isolation material.20. The memory device of claim 19 wherein a width of the pore is abouttwice the width of the overhang of the margin of the opening in the etchstop layer.
 21. A method for forming an electrode for a memory cell,comprising providing a dielectric fill over a memory element; providingan etch stop layer over the dielectric fill; forming a via through thedielectric fill and an opening through the etch stop layer, wherein amargin of the etch stop layer opening overhangs an edge of thedielectric fill via; depositing a dielectric form material in the via,whereby a void is formed in the dielectric form material;anisotropically etching the form material forming a pore in the formmaterial, exposing a small area of the surface of the memory element;and depositing an electrode material in the pore.
 22. The method ofclaim 21 wherein the form material comprises a thermal isolationmaterial.
 23. The method of claim 21 wherein forming the via comprisesremoving a portion of the dielectric fill beneath the margin of the etchstop layer opening.
 24. The method of claim 21 wherein a width of thevoid is about twice a width of the margin.
 25. The method of claim 21wherein a width of the small area of the surface of the memory elementis about twice a width of the margin.
 26. A method for making a memorycell device, comprising: providing a substrate; forming a bottomelectrode layer over a surface of the substrate; forming a memorymaterial layer over the bottom electrode layer; patterning the memorymaterial layer and the bottom electrode layer to form a memory elementand a bottom electrode; forming an intermetal dielectric fill layer overthe memory element and the bottom electrode and the substrate; formingan etch stop layer over the intermetal dielectric fill layer; forming avia through the etch stop layer and the dielectric fill layer to exposean area of the memory element, the via including an opening in the etchstop layer; removing a quantity of dielectric fill material from wallsof the via, forming a cavity and resulting in an undercut beneath themargin of the opening in the etch stop layer; depositing a thermalisolation material in the cavity over the memory material, whereby avoid is formed in the thermal isolation material; anisotropicallyetching the thermal isolation material to expose a small area of thesurface of the memory material, forming a pore in the thermal isolationmaterial adjacent the memory material and a wider cavity in theisolation material; and forming a top electrode by depositing anelectrode material in the pore and the wider cavity.
 27. The method ofclaim 2 wherein forming the memory material layer comprises depositing amaterial having at least two solid phases.
 28. The device of claim 27wherein forming the memory material layer comprises depositing amaterial having at least two solid phases, said solid phases beingreversibly inducible by a voltage applied across the bottom and topelectrodes.
 29. The device of claim 27 wherein forming the memorymaterial layer comprises depositing a material having at least two solidphases, said solid phases including a generally amorphous phase and agenerally crystalline phase.
 30. The device of claim 27 wherein formingthe memory material layer comprises depositing an alloy including acombination of Ge, Sb, and Te.
 31. The device of claim 27 whereinforming the memory material layer comprises depositing an alloyincluding a combination of two or more materials from the group Ge, Sb,Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.
 32. The method ofclaim 26 wherein forming the via through the etch stop layer and thedielectric fill layer comprises a mask and etch process.
 33. The methodof claim 26 wherein removing the quantity of dielectric fill materialcomprises a wet etch process.
 34. The method of claim 26 wherein formingthe top electrode comprises forming a liner in the narrow hole and thewider cavity, and forming a core over the liner.
 35. The method of claim26 wherein removing a quantity of dielectric fill material from walls ofthe via results in the undercut having a width in a range about 5 nm toabout 50 nm.
 36. The method of claim 26 wherein removing a quantity ofdielectric fill material from walls of the via results in the undercuthaving a width in a range about 10 nm to about 25 nm.
 37. The method ofclaim 26 wherein removing a quantity of dielectric fill material fromwalls of the via results in the undercut having a width about 15 nm. 38.The method of claim 21 wherein a width of the void is about twice awidth of the undercut.
 39. The method of claim 21 wherein a width of thesmall area of the surface of the memory element is about twice a widthof the undercut.
 40. A method for manufacturing a memory cell,comprising: forming a etch stop layer on a substrate; forming a lowerlayer of dielectric material on the etch stop layer; forming an upperlayer of dielectric material on the lower layer; forming an openingthrough the upper layer and lower layers to expose a surface of thesubstrate, the opening comprising a first, upper opening segment formedwithin the upper layer, a second, lower opening segment formed withinthe lower layer, the first and second opening segments having first andsecond widths, the upper layer having an overhanging portion extendinginto the opening so that the first width is less than the second width;depositing a fill material by a process in the opening, causingformation of a void centered within the opening, and having a widthdetermined by the difference between the first and second widths;anisotropically etching the fill material to open the void and thencontinuing to anistropically etch the fill material to expose thesubstrate in an area having a width substantially equal to the width ofthe void, and stopping the etching to leave a sidewall of fill materialon the sides of the opening in the second opening segment; etchingthrough the etch stop layer to define an electrode opening aligned withthe sidewall of fill material; and depositing electrode material in theelectrode opening to form an electrode aligned with the sidewall of fillmaterial.
 41. The method according to claim 40 wherein the openingforming step comprises increasing the volume of the upper layer.
 42. Themethod according to claim 40 wherein the opening forming step comprisesetching back the lower layer.
 43. The method according to claim 40wherein the opening forming step is carried out lithographically in amanner to create a minimum lithographic size opening for the openingforming step.
 44. The method according to claim 40 wherein the openingforming step comprises: selecting a material for the upper layer thatincreases its volume when subjected to the process; selecting a materialfor the lower layer that does not increase its volume when subjected tothe chosen process; forming the opening through the upper layer andlower layers to expose the surface of the substrate, the openingcomprising the first, upper opening segment and the second, loweropening segment; and subjecting the upper and lower layers to the chosenprocess thereby increasing the volume of the upper layer and creatingthe overhanging portion extending into the opening while not increasingthe volume of the lower layer.
 45. The method according to claim 44wherein the selecting steps comprise selecting silicon for the upperlayer and selecting an oxide for the lower layer.
 46. The methodaccording to claim 40 wherein the opening forming comprises: selecting amaterial for the upper layer that does not decrease its volume whensubjected to the process; selecting a material for the lower layer thatis etched back and thereby decreases its volume when subjected to thechosen process; forming the opening through the upper and lower layersto expose the surface of the substrate, the opening comprising thefirst, upper opening segment and the second, lower opening segment; andsubjecting the upper and lower layers to the chosen process therebyetching back the lower layer thereby decreasing the volume of the lowerlayer while not decreasing the volume of the upper layer therebycreating the overhanging portion extending into the opening.
 47. Themethod according to claim 46 wherein the selecting steps compriseselecting silicon nitride for the upper layer and selecting siliconoxide for the lower layer.
 48. The method according to claim 40 whereinthe fill material comprises silicon.
 49. The method according to claim40 wherein the fill material comprises a dielectric material.